1. Field of the Invention
This invention relates to a CMOS logic circuit having inputs biased to a predetermined logic level.
More particularly, the invention relates to a sub-family of high-speed CMOS logic circuits (HCMOS) adapted to replace, in many applications, TTL (Transistor-Transistor Logic) technology devices including low-power Schottky transistors (LSTTL). The description herein below will make reference to this field of application for convenience of illustration.
2. Discussion of Related Art
As is known, CMOS logic circuits are currently gaining increased acceptance on account of their negligible electric current, and hence power, requirements for nearly the same performance as the logic families of the TTL or LSTTL types.
The single drawback of CMOS devices, when used as substitutes for LSTTLs devices, may possibly be that the threshold voltage value Vin whereat commutation of the circuit is established is one half the value of the supply voltage Vdd, the latter lying within the range of 2 to 6 Volts for a HCMOS.
In order to be compatible with TTL logic families, however, the threshold voltage should be a smaller value, e.g. close to a value of 1.3 Volts with a voltage supply in the 4.5 to 5.5 Volts range (as is typical of the LSTTL family).
To fill this requirement, CMOS logic circuits have been proposed which have on their input side at least one inverter with a p-channel MOS of the implanted type and an n-channel MOS. That approach allows the threshold voltage to be lowered, both on account of the p-channel MOS having a higher trigger voltage Vth and because the ratio of the B parameters of the two transistors can be manipulated.
In this way, the threshold voltage of the CMOS circuit can be brought to a compatible value with that of the LSTTL families.
However, with many applications, there is the added requirement that CMOS circuit inputs should be biased to a predetermined logic level dependent on their functions. This requirement is more heavily felt in peripheral units and computer bus connections.
Now, where an LSTTL technology circuit is to be exchanged in applications for which the electronic board designer's goal is to impose a predetermined logic value on the inputs left floating, it is necessary that a bias network comprising external resistances with a high value in the 100 to 300 kOhms be associated with the HCMOS circuit.
All of these requirements are against the current trend toward lower assembling costs, size and power consumption of electronic boards. Such demands are specially notable in the instance of miniaturized assembly procedures carried out using a Surface Mounting technology and of battery powered systems.
A possible remedy to this drawback could be that of incorporating, to the CMOS integrated circuit, a resistance of an appropriate value to each input, but it is quite apparent that such a solution would be unacceptable in terms of occupied silicon area due to the large value that the resistance ought to have.
The underlying technical problem of this invention is to provide a logic circuit of the CMOS type which has such structural and functional characteristics as to overcome the aforementioned drawbacks and affords full compatibility with logic families of the TTL or LSTTL type, to the point of making it feasible to exchange between different family circuits.
Another object of the invention is to reduce the assembly costs, as well as the size and power consumption of electronic boards incorporating the logic circuits. Thus, the reliability of the inventive circuit can be improved over that of the two discrete circuits connected on a board, to provide a single integrated circuit whose overall performance can be guaranteed by the manufacturer.
The solutive idea on which this invention stands is one of providing an equivalent bias resistor within the CMOS technology integrated circuit.